From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Sat, 13 Aug 2022 14:48:51 +0200 Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy There are certain race condition when the SGMII_PHYA_PWD register still contains 0x9 which prevents the SGMII from working properly. The SGMII still shows link but no traffic can flow. Signed-off-by: Alexander Couzens --- drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct val |= SGMII_AN_RESTART; regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); - regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val &= ~SGMII_PHYA_PWD; - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); return 0; @@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); /* Release PHYA power down state */ - regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); - val &= ~SGMII_PHYA_PWD; - regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); + regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); return 0; }